RISC-V
A headline
Possible motto/subline…
Developed, upstreamed and still maintain RISC-V 64-bit support for the Zephyr RTOS
Three successful projects to upstream RISC-V features to industry standard QEMU emulator
Over half a dozen semiconductor customers engaged with BayLibre on their RISC-V based designs
Esperanto
Axiado
Rivos
RISE
Meta
SiFive
TI
(Renesas forthcoming)
A headline
BayLibre delivers deep expertise across the RISC-V software stack, from early hardware bring-up to optimized production systems. We work closely with silicon vendors, IP providers, and product teams to enable RISC-V platforms on Linux, embedded Linux, and RTOS environments. Our engineers operate across bootloaders, kernels, BSPs, compilers, and low-level firmware, ensuring correct enablement of cores, memory subsystems, interrupts, power management, and platform-specific extensions.
Beyond initial enablement, BayLibre helps customers turn RISC-V platforms into performant, maintainable, and upstream-ready systems. We optimize compiler toolchains (GCC and LLVM), validate ABI and ISA extensions, and address real-world constraints such as determinism, long-term support, and multi-vendor portability. By aligning closely with upstream communities and the broader RISC-V ecosystem, we help reduce technical debt while accelerating time-to-market on both standard and custom RISC-V implementations.
Our services include:
RISC-V BSP development and hardware bring-up (bootloader, kernel, firmware)
GCC and LLVM toolchain enablement and optimization for RISC-V targets
Linux, RTOS, and bare-metal integration on RISC-V platforms
Upstreaming, long-term maintenance, and ecosystem alignment
